Field of the Invention
The present invention relates to a memory access technique.
Description of the Related Art
As the degree of integration of semiconductors increases, various processors are integrated in one LSI chip. When integrating various processors in one LSI chip, a configuration in which these processors in the chip share a DRAM connected outside the LSI chip is widely adopted to suppress the cost to be low.
At this time, the order of addresses at which the memory is accessed (access pattern) when the respective processors access the DRAM are sometimes different. Along with this, it is necessary to appropriately perform page close in the page mode of the DRAM so as to shorten the DRAM access time and obtain high performance even when a different access pattern is used.
Recent DRAMs have a page mode capable of shortening the access time. A DRAM is constituted by a plurality of banks, and each bank includes a plurality of pages. The DRAM selects a page to be accessed in accordance with a bank selection signal and ROW address, opens it, and designates a read or write destination address in accordance with designation of the next COLUMN address.
By using the page mode, when the same page in the bank of the DRAM is accessed (when a page hit occurs), the page can be accessed in a short time. However, when another page in the bank of the DRAM is accessed (when a page miss occurs), precharge is performed to close the currently accessed page, then a new ROW address is designated, and the page is opened and accessed.
FIGS. 1A and 1B show the procedures of the DRAM access. The DRAM opens a page in accordance with ACT, designates a page in accordance with CMD, makes a write or read access, and closes the page in accordance with PRE.
FIG. 1A shows a case in which the first access and second access target the same bank and the same page, and a page hit occurs in the second access. In this case, a page is opened in accordance with ACT 120, and the first access is made in accordance with CMD 121. After that, CMD 122 is issued, and the second access can be made without closing the page or opening another page.
FIG. 1B shows a case in which the first access and second access target different pages of the same bank, and a page miss occurs in the second access. At this time, first, a page is opened in accordance with ACT 123, and the first access is made in accordance with CMD 124. Then, the page is closed in accordance with PRE 125, a page is opened for the second access in accordance with ACT 126, and the second access is made in accordance with CMD 127. Hence, a page miss penalty 128 is generated by the ACT and PRE.
To improve the memory access speed, it is important to reduce penalties upon page misses by decreasing page misses.
Which of a page hit and miss occurs depends on the memory access pattern (access order) of a processor and the page allocation. For example, in an access pattern in the raster direction shown in FIG. 2, the address increases continuously. In a rectangle order access pattern shown in FIG. 3, the address increases continuously in the X direction, and then increases in the Y direction, so the address increases discontinuously.
In this manner, when a plurality of access patterns are used, page allocation to the bits of a ROW address and COLUMN address is performed so that a page remains unchanged even if the page is increased in either the X direction or Y direction, in order to increase the memory access speed. For example, in FIG. 4, when the page size is 1 KB, as a frame buffer, 16 pixels in the X direction×16 pixels in the Y direction form an identical page, where one pixel is comprised of 32 bits (4 bytes).
Japanese Patent Laid-Open Nos. 2000-331476 and 2006-127110 disclose techniques for controlling issuing of page close in accordance with a memory access pattern. Japanese Patent Laid-Open No. 2000-331476 discloses a technique in which a memory controller detects whether a page subjected to the current memory access and a page subjected to the next memory access are the same in the address queue, thereby performing close at an appropriate timing. Japanese Patent Laid-Open No. 2006-127110 discloses a technique in which when a plurality of bus masters have different orders of addresses to be accessed in a memory, a memory controller can detect the end of a burst access for each bus master. In the technique disclosed in Japanese Patent Laid-Open No. 2006-127110, page close, and open of a page to be referred to in a subsequent memory access are performed at the end of a burst access for each master device.
A plurality of processors existing in a system and having different memory access patterns is becoming popular. In terms of proper control of page close, the memory controller in Japanese Patent Laid-Open No. 2000-331476 cannot perform proper control if the next memory access has not arrived, because this memory controller uses the next memory access for detecting a page change. Further, the technique in Japanese Patent Laid-Open No. 2000-331476 increases the circuit scale for detecting a page change. The memory controller in Japanese Patent Laid-Open No. 2006-127110 performs page close control only at the end of a burst access. Thus, page close control when the page changes during a burst access becomes improper, and the memory access time becomes long.
The present invention has been made to solve the above-described problems, and provides a technique of shortening the memory access time with a simple arrangement.